1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a wordline driving circuit in a semiconductor memory device which is capable of removing noise from wordlines associated therewith when those wordlines are not being driven.
2. Description of Related Art
FIG. 1 illustrates a portion of a conventional wordline driving circuit. As shown, a sub-row decoder 1 is connected to a plurality of subwordline selectors 2. Each of the subwordline selectors 2 is connected to a wordline W/L and an enable line WD. The structure of each subwordline selector 2 is the same. Therefore, the structure and operation of only the subwordline selector 2 for the first wordline W/L1 will be described.
As shown in FIG. 1, the subwordline selector 2 for the first wordline W/L1 includes a PMOS transistor MP connected in series with an NMOS transistor MN between the first enable line WD and ground. The gates of the PMOS and NMOS transistors MP and MN receive the row signal output by the sub-row decoder 1, and the junction between the PMOS and NMOS transistors MP and MN drive the first wordline W/L1.
In operation, the sub-row decoder 1 decodes an address and generates a row signal. The row signal will be logic high if a memory cell specified in the address is not a memory cell associated with any of the subwordline selectors 2 connected to the sub-row decoder 1. However, if the memory cell identified in the address is associated with one of the subwordline selectors 2, the sub-row decoder 1 generates a logic low row signal.
When the sub-row decoder 1 generates a logic high row signal, the NMOS transistor in each of the subwordline selectors 2 turns on and pulls the associated wordline W/L to logic low. When the sub-row decoder 1 generates a logic low row signal, the NMOS transistor MN is off, and the PMOS transistor MP turns on. Accordingly, the PMOS transistor MP in each subwordline selector 2 supplies the associated enable signal WD to the associated wordline W/L. One of the enable signals WD will be logic high and the remainder low such that only one of the wordlines W/L is driven.
Unfortunately, however, due to the reduction in memory cell size and the design considerations resulting therefrom, noise can develop on a wordline W/L even when supplied with a logic high row signal such that the wordline W/L is erroneously driven.